The invention is directed to an improved approach for placing core content for electronic designs.
A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer.
Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
An integrated circuit designer may use a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Verification may include, for example, design rule checking to verify compliance with rules established for various IC parameters.
The EDA tools may also be used to perform early stage analysis and examinations of an electronic design. For example, the process of performing chip planning can be greatly facilitated if the designer or chip planning tool can predict the expected die size and configuration for the IC product. However, the die size and configuration of the IC product is significantly affected by the configuration of the I/O ring and cores needed to support the IC product. The I/O ring is a top-level component within which all I/O related logic is instantiated, and is usually positioned around the periphery of the IC chip. Typical components on the I/O ring include, for example, I/O cells, power and ground cells, boundary scan registers (BSRs), pin structures, and/or other glue-logic structures. The IC core typically resides within the boundaries of the I/O ring, with the core typically including the internal blocks and connectivity of the IC chip.
For planning purposes, it is very desirable for engineers and architects to be able to obtain and visually review accurate estimates of the I/O ring and IC core configuration for the final IC product. One reason this functionality is useful is because this type of visualization and estimation allows the engineer or architect to know the required die size for the product. For example, consider that the I/O ring creates the peripheral boundary of the IC chip, which means that the amount of space available for the IC core is greatly affected by the size of the I/O ring. Therefore, the size and dimensions of the die are also greatly affected by the required dimensions of the I/O ring and the IC core structures. The size of the die for the IC product must be large enough to hold the required I/O ring structures as well as the core structures. Clearly, the most efficient die size is the situation when the dimensions of the minimum I/O ring periphery creates enough interior space to exactly match the required space of the core. If the total size of the periphery for the I/O ring is greater than what is needed to implement the core, the design is said to be “I/O limited”. A design is “core limited” if the core requires more space than the minimum periphery required to implement the I/O ring.
The general problem addressed by embodiments of the invention pertains to placement of core structures and objects within the core area that is defined by inner periphery of an I/O ring. An I/O ring design will normally include a number of I/O objects having different sizes and dimensions. Because of the differing sizes and dimensions for the I/O ring objects, the inner periphery of that I/O ring will contain a number of non-uniform surfaces. Those non-uniform surfaces will collectively create a very complex shape for the core area.
An example I/O ring design 760 is illustrated in FIG. 7. The I/O ring design 760 includes numerous types of I/Os 700, 702, 704, 706, 708, 710, 712, 716, 718, 720, 722, and 724, where each of the I/Os have differing shapes and sizes, resulting in a core area 762 that has non-uniform surfaces on all of its top, right, bottom, and left sides. The issue is that the designer needs to place the collection 770 of core objects A-K into that non-uniform core area 762. This becomes a very difficult problem given the complex nature and shape of the core area 762, along with the fact that the core objects A-K may includes different types of structures, such as hard IP objects/blocks that cannot be re-shaped.
A “full flat” approach can be taken in an attempt to solve this problem. The full flat approach uses a fully detailed netlist, which is flattened and where each of the design shapes are placed into a core area as a set of closely placed rectilinear polygons. The problem with this approach is that since it only works with the fully detailed netlist, it cannot be used to perform early stage design analysis. Moreover, this approach is very costly and expensive since it operates upon a very large number of objects for the core placement. In addition, this approach does not provide any certainty that shapes/blocks will end up together or at preferred locations in the core, even if the preferred proximities or locations are helpful to the design performance. For example, it is likely that fitment of certain objects into the core will require those objects to be formed into odd or elongated shapes that stretch across different portions of the core area.
Therefore, there is a need for an improved approach to implement placement of objects into a core area of an I/O ring design.